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103 lines
4.1 KiB
C++
103 lines
4.1 KiB
C++
#ifndef USER_MODE_CLEAR_CACHE_TOOL_ARM64_H
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#define USER_MODE_CLEAR_CACHE_TOOL_ARM64_H
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#include "core/arch/Cpu.h"
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#include "PlatformInterface/globals.h"
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class CacheLineSizes {
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public:
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CacheLineSizes() {
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// Copy the content of the cache type register to a core register.
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__asm__ __volatile__("mrs %x[ctr], ctr_el0" // NOLINT
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: [ctr] "=r"(cache_type_register_));
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}
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uint32_t icache_line_size() const {
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return ExtractCacheLineSize(0);
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}
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uint32_t dcache_line_size() const {
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return ExtractCacheLineSize(16);
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}
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private:
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uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
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// The cache type register holds the size of cache lines in words as a
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// power of two.
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return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xF);
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}
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uint32_t cache_type_register_;
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};
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void CpuFeatures::FlushICache(void *startp, void *endp) {
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// The code below assumes user space cache operations are allowed. The goal
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// of this routine is to make sure the code generated is visible to the I
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// side of the CPU.
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#if HOST_OS_IOS
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// Precompilation never patches code so there should be no I cache flushes.
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CpuFeatures::ClearCache(startp, endp);
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#else
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uintptr_t start = reinterpret_cast<uintptr_t>(startp);
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// Sizes will be used to generate a mask big enough to cover a pointer.
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CacheLineSizes sizes;
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uintptr_t dsize = sizes.dcache_line_size();
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uintptr_t isize = sizes.icache_line_size();
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// Cache line sizes are always a power of 2.
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uintptr_t dstart = start & ~(dsize - 1);
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uintptr_t istart = start & ~(isize - 1);
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uintptr_t end = reinterpret_cast<uintptr_t>(endp);
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__asm__ __volatile__( // NOLINT
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// Clean every line of the D cache containing the target data.
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"0: \n\t"
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// dc : Data Cache maintenance
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// c : Clean
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// i : Invalidate
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// va : by (Virtual) Address
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// c : to the point of Coherency
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// See ARM DDI 0406B page B2-12 for more information.
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// We would prefer to use "cvau" (clean to the point of unification) here
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// but we use "civac" to work around Cortex-A53 errata 819472, 826319,
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// 827319 and 824069.
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"dc civac, %[dline] \n\t"
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"add %[dline], %[dline], %[dsize] \n\t"
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"cmp %[dline], %[end] \n\t"
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"b.lt 0b \n\t"
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// Barrier to make sure the effect of the code above is visible to the rest
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// of the world.
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// dsb : Data Synchronisation Barrier
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// ish : Inner SHareable domain
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// The point of unification for an Inner Shareable shareability domain is
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// the point by which the instruction and data caches of all the processors
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// in that Inner Shareable shareability domain are guaranteed to see the
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// same copy of a memory location. See ARM DDI 0406B page B2-12 for more
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// information.
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"dsb ish \n\t"
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// Invalidate every line of the I cache containing the target data.
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"1: \n\t"
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// ic : instruction cache maintenance
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// i : invalidate
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// va : by address
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// u : to the point of unification
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"ic ivau, %[iline] \n\t"
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"add %[iline], %[iline], %[isize] \n\t"
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"cmp %[iline], %[end] \n\t"
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"b.lt 1b \n\t"
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// Barrier to make sure the effect of the code above is visible to the rest
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// of the world.
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"dsb ish \n\t"
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// Barrier to ensure any prefetching which happened before this code is
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// discarded.
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// isb : Instruction Synchronisation Barrier
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"isb \n\t"
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: [dline] "+r"(dstart), [iline] "+r"(istart)
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: [dsize] "r"(dsize), [isize] "r"(isize), [end] "r"(end)
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// This code does not write to memory but without the dependency gcc might
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// move this code before the code is generated.
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: "cc", "memory"); // NOLINT
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#endif
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}
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#endif
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