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53 lines
No EOL
1.5 KiB
C++
53 lines
No EOL
1.5 KiB
C++
#ifndef USER_MODE_CLEAR_CACHE_TOOL_H
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#define USER_MODE_CLEAR_CACHE_TOOL_H
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#include "core/arch/Cpu.h"
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#include "PlatformInterface/globals.h"
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#if !HOST_OS_IOS
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#include <sys/syscall.h> // for cache flushing.
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#endif
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void CpuFeatures::FlushICache(void *startp, void *endp) {
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#if HOST_OS_IOS
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// Precompilation never patches code so there should be no I cache flushes.
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CpuFeatures::ClearCache(startp, endp);
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#else
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register uint32_t beg asm("r0") = reinterpret_cast<uint32_t>(startp);
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register uint32_t end asm("r1") = reinterpret_cast<uint32_t>(endp);
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register uint32_t flg asm("r2") = 0;
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#ifdef __clang__
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// This variant of the asm avoids a constant pool entry, which can be
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// problematic when LTO'ing. It is also slightly shorter.
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register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
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asm volatile("svc 0\n" : : "r"(beg), "r"(end), "r"(flg), "r"(scno) : "memory");
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#else
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// Use a different variant of the asm with GCC because some versions doesn't
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// support r7 as an asm input.
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asm volatile(
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// This assembly works for both ARM and Thumb targets.
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// Preserve r7; it is callee-saved, and GCC uses it as a frame pointer for
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// Thumb targets.
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" push {r7}\n"
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// r0 = beg
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// r1 = end
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// r2 = flags (0)
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" ldr r7, =%c[scno]\n" // r7 = syscall number
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" svc 0\n"
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" pop {r7}\n"
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:
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: "r"(beg), "r"(end), "r"(flg), [scno] "i"(__ARM_NR_cacheflush)
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: "memory");
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#endif
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#endif
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}
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#endif |