discourse/lib/highlight_js/assets/lang/verilog.js

hljs.registerLanguage("verilog",function(e){return{aliases:["v"],cI:!1,k:{keyword:"always and assign begin buf bufif0 bufif1 case casex casez cmos deassign default defparam disable edge else end endcase endfunction endmodule endprimitive endspecify endtable endtask event for force forever fork function if ifnone initial inout input join macromodule module nand negedge nmos nor not notif0 notif1 or output parameter pmos posedge primitive pulldown pullup rcmos release repeat rnmos rpmos rtran rtranif0 rtranif1 specify specparam table task timescale tran tranif0 tranif1 wait while xnor xor highz0 highz1 integer large medium pull0 pull1 real realtime reg scalared signed small strong0 strong1 supply0 supply0 supply1 supply1 time tri tri0 tri1 triand trior trireg vectored wand weak0 weak1 wire wor"},c:[e.CBCM,e.CLCM,e.QSM,{cN:"number",b:"(\\b((\\d'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+))|(\\B(('(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F_]+))|(\\b([0-9xzXZ_])+)",c:[e.BE],r:0},{cN:"variable",b:"#\\((?!parameter).+\\)"}]}});