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395 lines
15 KiB
C
395 lines
15 KiB
C
/*
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* Copyright (c) 2007-2016 Apple, Inc. All rights reserved.
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* Copyright (c) 2000 Apple Computer, Inc. All rights reserved.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
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*
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* This file contains Original Code and/or Modifications of Original Code
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* as defined in and that are subject to the Apple Public Source License
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* Version 2.0 (the 'License'). You may not use this file except in
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* compliance with the License. The rights granted to you under the License
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* may not be used to create, or enable the creation or redistribution of,
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* unlawful or unlicensed copies of an Apple operating system, or to
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* circumvent, violate, or enable the circumvention or violation of, any
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* terms of an Apple operating system software license agreement.
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*
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* Please obtain a copy of the License at
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* http://www.opensource.apple.com/apsl/ and read it before using this file.
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*
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* The Original Code and all software distributed under the License are
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* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
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* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
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* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
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* Please see the License for the specific language governing rights and
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* limitations under the License.
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*
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* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
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*/
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/*
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* Mach Operating System
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* Copyright (c) 1991,1990,1989,1988,1987 Carnegie Mellon University
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
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* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/* File: machine.h
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* Author: Avadis Tevanian, Jr.
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* Date: 1986
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*
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* Machine independent machine abstraction.
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*/
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#ifndef _MACH_MACHINE_H_
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#define _MACH_MACHINE_H_
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#ifndef __ASSEMBLER__
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#include <stdint.h>
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#include <mach/machine/vm_types.h>
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#include <mach/boolean.h>
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typedef integer_t cpu_type_t;
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typedef integer_t cpu_subtype_t;
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typedef integer_t cpu_threadtype_t;
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#define CPU_STATE_MAX 4
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#define CPU_STATE_USER 0
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#define CPU_STATE_SYSTEM 1
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#define CPU_STATE_IDLE 2
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#define CPU_STATE_NICE 3
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/*
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* Capability bits used in the definition of cpu_type.
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*/
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#define CPU_ARCH_MASK 0xff000000 /* mask for architecture bits */
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#define CPU_ARCH_ABI64 0x01000000 /* 64 bit ABI */
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#define CPU_ARCH_ABI64_32 0x02000000 /* ABI for 64-bit hardware with 32-bit types; LP32 */
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/*
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* Machine types known by all.
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*/
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#define CPU_TYPE_ANY ((cpu_type_t) -1)
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#define CPU_TYPE_VAX ((cpu_type_t) 1)
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/* skip ((cpu_type_t) 2) */
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/* skip ((cpu_type_t) 3) */
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/* skip ((cpu_type_t) 4) */
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/* skip ((cpu_type_t) 5) */
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#define CPU_TYPE_MC680x0 ((cpu_type_t) 6)
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#define CPU_TYPE_X86 ((cpu_type_t) 7)
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#define CPU_TYPE_I386 CPU_TYPE_X86 /* compatibility */
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#define CPU_TYPE_X86_64 (CPU_TYPE_X86 | CPU_ARCH_ABI64)
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/* skip CPU_TYPE_MIPS ((cpu_type_t) 8) */
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/* skip ((cpu_type_t) 9) */
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#define CPU_TYPE_MC98000 ((cpu_type_t) 10)
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#define CPU_TYPE_HPPA ((cpu_type_t) 11)
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#define CPU_TYPE_ARM ((cpu_type_t) 12)
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#define CPU_TYPE_ARM64 (CPU_TYPE_ARM | CPU_ARCH_ABI64)
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#define CPU_TYPE_ARM64_32 (CPU_TYPE_ARM | CPU_ARCH_ABI64_32)
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#define CPU_TYPE_MC88000 ((cpu_type_t) 13)
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#define CPU_TYPE_SPARC ((cpu_type_t) 14)
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#define CPU_TYPE_I860 ((cpu_type_t) 15)
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/* skip CPU_TYPE_ALPHA ((cpu_type_t) 16) */
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/* skip ((cpu_type_t) 17) */
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#define CPU_TYPE_POWERPC ((cpu_type_t) 18)
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#define CPU_TYPE_POWERPC64 (CPU_TYPE_POWERPC | CPU_ARCH_ABI64)
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/* skip ((cpu_type_t) 19) */
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/*
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* Machine subtypes (these are defined here, instead of in a machine
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* dependent directory, so that any program can get all definitions
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* regardless of where is it compiled).
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*/
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/*
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* Capability bits used in the definition of cpu_subtype.
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*/
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#define CPU_SUBTYPE_MASK 0xff000000 /* mask for feature flags */
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#define CPU_SUBTYPE_LIB64 0x80000000 /* 64 bit libraries */
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/*
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* Object files that are hand-crafted to run on any
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* implementation of an architecture are tagged with
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* CPU_SUBTYPE_MULTIPLE. This functions essentially the same as
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* the "ALL" subtype of an architecture except that it allows us
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* to easily find object files that may need to be modified
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* whenever a new implementation of an architecture comes out.
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*
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* It is the responsibility of the implementor to make sure the
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* software handles unsupported implementations elegantly.
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*/
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#define CPU_SUBTYPE_MULTIPLE ((cpu_subtype_t) -1)
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#define CPU_SUBTYPE_LITTLE_ENDIAN ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_BIG_ENDIAN ((cpu_subtype_t) 1)
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/*
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* Machine threadtypes.
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* This is none - not defined - for most machine types/subtypes.
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*/
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#define CPU_THREADTYPE_NONE ((cpu_threadtype_t) 0)
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/*
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* VAX subtypes (these do *not* necessary conform to the actual cpu
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* ID assigned by DEC available via the SID register).
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*/
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#define CPU_SUBTYPE_VAX_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_VAX780 ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_VAX785 ((cpu_subtype_t) 2)
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#define CPU_SUBTYPE_VAX750 ((cpu_subtype_t) 3)
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#define CPU_SUBTYPE_VAX730 ((cpu_subtype_t) 4)
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#define CPU_SUBTYPE_UVAXI ((cpu_subtype_t) 5)
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#define CPU_SUBTYPE_UVAXII ((cpu_subtype_t) 6)
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#define CPU_SUBTYPE_VAX8200 ((cpu_subtype_t) 7)
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#define CPU_SUBTYPE_VAX8500 ((cpu_subtype_t) 8)
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#define CPU_SUBTYPE_VAX8600 ((cpu_subtype_t) 9)
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#define CPU_SUBTYPE_VAX8650 ((cpu_subtype_t) 10)
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#define CPU_SUBTYPE_VAX8800 ((cpu_subtype_t) 11)
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#define CPU_SUBTYPE_UVAXIII ((cpu_subtype_t) 12)
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/*
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* 680x0 subtypes
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*
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* The subtype definitions here are unusual for historical reasons.
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* NeXT used to consider 68030 code as generic 68000 code. For
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* backwards compatability:
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*
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* CPU_SUBTYPE_MC68030 symbol has been preserved for source code
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* compatability.
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*
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* CPU_SUBTYPE_MC680x0_ALL has been defined to be the same
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* subtype as CPU_SUBTYPE_MC68030 for binary comatability.
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*
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* CPU_SUBTYPE_MC68030_ONLY has been added to allow new object
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* files to be tagged as containing 68030-specific instructions.
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*/
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#define CPU_SUBTYPE_MC680x0_ALL ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_MC68030 ((cpu_subtype_t) 1) /* compat */
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#define CPU_SUBTYPE_MC68040 ((cpu_subtype_t) 2)
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#define CPU_SUBTYPE_MC68030_ONLY ((cpu_subtype_t) 3)
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/*
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* I386 subtypes
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*/
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#define CPU_SUBTYPE_INTEL(f, m) ((cpu_subtype_t) (f) + ((m) << 4))
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#define CPU_SUBTYPE_I386_ALL CPU_SUBTYPE_INTEL(3, 0)
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#define CPU_SUBTYPE_386 CPU_SUBTYPE_INTEL(3, 0)
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#define CPU_SUBTYPE_486 CPU_SUBTYPE_INTEL(4, 0)
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#define CPU_SUBTYPE_486SX CPU_SUBTYPE_INTEL(4, 8) // 8 << 4 = 128
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#define CPU_SUBTYPE_586 CPU_SUBTYPE_INTEL(5, 0)
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#define CPU_SUBTYPE_PENT CPU_SUBTYPE_INTEL(5, 0)
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#define CPU_SUBTYPE_PENTPRO CPU_SUBTYPE_INTEL(6, 1)
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#define CPU_SUBTYPE_PENTII_M3 CPU_SUBTYPE_INTEL(6, 3)
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#define CPU_SUBTYPE_PENTII_M5 CPU_SUBTYPE_INTEL(6, 5)
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#define CPU_SUBTYPE_CELERON CPU_SUBTYPE_INTEL(7, 6)
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#define CPU_SUBTYPE_CELERON_MOBILE CPU_SUBTYPE_INTEL(7, 7)
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#define CPU_SUBTYPE_PENTIUM_3 CPU_SUBTYPE_INTEL(8, 0)
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#define CPU_SUBTYPE_PENTIUM_3_M CPU_SUBTYPE_INTEL(8, 1)
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#define CPU_SUBTYPE_PENTIUM_3_XEON CPU_SUBTYPE_INTEL(8, 2)
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#define CPU_SUBTYPE_PENTIUM_M CPU_SUBTYPE_INTEL(9, 0)
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#define CPU_SUBTYPE_PENTIUM_4 CPU_SUBTYPE_INTEL(10, 0)
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#define CPU_SUBTYPE_PENTIUM_4_M CPU_SUBTYPE_INTEL(10, 1)
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#define CPU_SUBTYPE_ITANIUM CPU_SUBTYPE_INTEL(11, 0)
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#define CPU_SUBTYPE_ITANIUM_2 CPU_SUBTYPE_INTEL(11, 1)
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#define CPU_SUBTYPE_XEON CPU_SUBTYPE_INTEL(12, 0)
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#define CPU_SUBTYPE_XEON_MP CPU_SUBTYPE_INTEL(12, 1)
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#define CPU_SUBTYPE_INTEL_FAMILY(x) ((x) & 15)
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#define CPU_SUBTYPE_INTEL_FAMILY_MAX 15
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#define CPU_SUBTYPE_INTEL_MODEL(x) ((x) >> 4)
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#define CPU_SUBTYPE_INTEL_MODEL_ALL 0
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/*
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* X86 subtypes.
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*/
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#define CPU_SUBTYPE_X86_ALL ((cpu_subtype_t)3)
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#define CPU_SUBTYPE_X86_64_ALL ((cpu_subtype_t)3)
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#define CPU_SUBTYPE_X86_ARCH1 ((cpu_subtype_t)4)
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#define CPU_SUBTYPE_X86_64_H ((cpu_subtype_t)8) /* Haswell feature subset */
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#define CPU_THREADTYPE_INTEL_HTT ((cpu_threadtype_t) 1)
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/*
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* Mips subtypes.
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*/
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#define CPU_SUBTYPE_MIPS_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_MIPS_R2300 ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_MIPS_R2600 ((cpu_subtype_t) 2)
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#define CPU_SUBTYPE_MIPS_R2800 ((cpu_subtype_t) 3)
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#define CPU_SUBTYPE_MIPS_R2000a ((cpu_subtype_t) 4) /* pmax */
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#define CPU_SUBTYPE_MIPS_R2000 ((cpu_subtype_t) 5)
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#define CPU_SUBTYPE_MIPS_R3000a ((cpu_subtype_t) 6) /* 3max */
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#define CPU_SUBTYPE_MIPS_R3000 ((cpu_subtype_t) 7)
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/*
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* MC98000 (PowerPC) subtypes
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*/
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#define CPU_SUBTYPE_MC98000_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_MC98601 ((cpu_subtype_t) 1)
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/*
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* HPPA subtypes for Hewlett-Packard HP-PA family of
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* risc processors. Port by NeXT to 700 series.
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*/
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#define CPU_SUBTYPE_HPPA_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_HPPA_7100 ((cpu_subtype_t) 0) /* compat */
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#define CPU_SUBTYPE_HPPA_7100LC ((cpu_subtype_t) 1)
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/*
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* MC88000 subtypes.
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*/
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#define CPU_SUBTYPE_MC88000_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_MC88100 ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_MC88110 ((cpu_subtype_t) 2)
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/*
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* SPARC subtypes
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*/
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#define CPU_SUBTYPE_SPARC_ALL ((cpu_subtype_t) 0)
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/*
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* I860 subtypes
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*/
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#define CPU_SUBTYPE_I860_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_I860_860 ((cpu_subtype_t) 1)
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/*
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* PowerPC subtypes
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*/
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#define CPU_SUBTYPE_POWERPC_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_POWERPC_601 ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_POWERPC_602 ((cpu_subtype_t) 2)
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#define CPU_SUBTYPE_POWERPC_603 ((cpu_subtype_t) 3)
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#define CPU_SUBTYPE_POWERPC_603e ((cpu_subtype_t) 4)
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#define CPU_SUBTYPE_POWERPC_603ev ((cpu_subtype_t) 5)
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#define CPU_SUBTYPE_POWERPC_604 ((cpu_subtype_t) 6)
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#define CPU_SUBTYPE_POWERPC_604e ((cpu_subtype_t) 7)
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#define CPU_SUBTYPE_POWERPC_620 ((cpu_subtype_t) 8)
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#define CPU_SUBTYPE_POWERPC_750 ((cpu_subtype_t) 9)
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#define CPU_SUBTYPE_POWERPC_7400 ((cpu_subtype_t) 10)
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#define CPU_SUBTYPE_POWERPC_7450 ((cpu_subtype_t) 11)
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#define CPU_SUBTYPE_POWERPC_970 ((cpu_subtype_t) 100)
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/*
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* ARM subtypes
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*/
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#define CPU_SUBTYPE_ARM_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_ARM_V4T ((cpu_subtype_t) 5)
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#define CPU_SUBTYPE_ARM_V6 ((cpu_subtype_t) 6)
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#define CPU_SUBTYPE_ARM_V5TEJ ((cpu_subtype_t) 7)
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#define CPU_SUBTYPE_ARM_XSCALE ((cpu_subtype_t) 8)
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#define CPU_SUBTYPE_ARM_V7 ((cpu_subtype_t) 9) /* ARMv7-A and ARMv7-R */
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#define CPU_SUBTYPE_ARM_V7F ((cpu_subtype_t) 10) /* Cortex A9 */
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#define CPU_SUBTYPE_ARM_V7S ((cpu_subtype_t) 11) /* Swift */
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#define CPU_SUBTYPE_ARM_V7K ((cpu_subtype_t) 12)
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#define CPU_SUBTYPE_ARM_V8 ((cpu_subtype_t) 13)
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#define CPU_SUBTYPE_ARM_V6M ((cpu_subtype_t) 14) /* Not meant to be run under xnu */
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#define CPU_SUBTYPE_ARM_V7M ((cpu_subtype_t) 15) /* Not meant to be run under xnu */
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#define CPU_SUBTYPE_ARM_V7EM ((cpu_subtype_t) 16) /* Not meant to be run under xnu */
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#define CPU_SUBTYPE_ARM_V8M ((cpu_subtype_t) 17) /* Not meant to be run under xnu */
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/*
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* ARM64 subtypes
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*/
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#define CPU_SUBTYPE_ARM64_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_ARM64_V8 ((cpu_subtype_t) 1)
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#define CPU_SUBTYPE_ARM64E ((cpu_subtype_t) 2)
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/* CPU subtype feature flags for ptrauth on arm64e platforms */
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#define CPU_SUBTYPE_ARM64_PTR_AUTH_MASK 0x0f000000
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#define CPU_SUBTYPE_ARM64_PTR_AUTH_VERSION(x) (((x) & CPU_SUBTYPE_ARM64_PTR_AUTH_MASK) >> 24)
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/*
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* ARM64_32 subtypes
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*/
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#define CPU_SUBTYPE_ARM64_32_ALL ((cpu_subtype_t) 0)
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#define CPU_SUBTYPE_ARM64_32_V8 ((cpu_subtype_t) 1)
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#endif /* !__ASSEMBLER__ */
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/*
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* CPU families (sysctl hw.cpufamily)
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*
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* These are meant to identify the CPU's marketing name - an
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* application can map these to (possibly) localized strings.
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* NB: the encodings of the CPU families are intentionally arbitrary.
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* There is no ordering, and you should never try to deduce whether
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* or not some feature is available based on the family.
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* Use feature flags (eg, hw.optional.altivec) to test for optional
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* functionality.
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*/
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#define CPUFAMILY_UNKNOWN 0
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#define CPUFAMILY_POWERPC_G3 0xcee41549
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#define CPUFAMILY_POWERPC_G4 0x77c184ae
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#define CPUFAMILY_POWERPC_G5 0xed76d8aa
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#define CPUFAMILY_INTEL_6_13 0xaa33392b
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#define CPUFAMILY_INTEL_PENRYN 0x78ea4fbc
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#define CPUFAMILY_INTEL_NEHALEM 0x6b5a4cd2
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#define CPUFAMILY_INTEL_WESTMERE 0x573b5eec
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#define CPUFAMILY_INTEL_SANDYBRIDGE 0x5490b78c
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#define CPUFAMILY_INTEL_IVYBRIDGE 0x1f65e835
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#define CPUFAMILY_INTEL_HASWELL 0x10b282dc
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#define CPUFAMILY_INTEL_BROADWELL 0x582ed09c
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#define CPUFAMILY_INTEL_SKYLAKE 0x37fc219f
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#define CPUFAMILY_INTEL_KABYLAKE 0x0f817246
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#if !defined(RC_HIDE_XNU_ICELAKE)
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#define CPUFAMILY_INTEL_ICELAKE 0x38435547
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#endif /* not RC_HIDE_XNU_ICELAKE */
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#if !defined(RC_HIDE_XNU_COMETLAKE)
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#define CPUFAMILY_INTEL_COMETLAKE 0x1cf8a03e
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#endif /* not RC_HIDE_XNU_COMETLAKE */
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#define CPUFAMILY_ARM_9 0xe73283ae
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#define CPUFAMILY_ARM_11 0x8ff620d8
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#define CPUFAMILY_ARM_XSCALE 0x53b005f5
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#define CPUFAMILY_ARM_12 0xbd1b0ae9
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#define CPUFAMILY_ARM_13 0x0cc90e64
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#define CPUFAMILY_ARM_14 0x96077ef1
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#define CPUFAMILY_ARM_15 0xa8511bca
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#define CPUFAMILY_ARM_SWIFT 0x1e2d6381
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#define CPUFAMILY_ARM_CYCLONE 0x37a09642
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#define CPUFAMILY_ARM_TYPHOON 0x2c91a47e
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#define CPUFAMILY_ARM_TWISTER 0x92fb37c8
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#define CPUFAMILY_ARM_HURRICANE 0x67ceee93
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#define CPUFAMILY_ARM_MONSOON_MISTRAL 0xe81e7ef6
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#define CPUFAMILY_ARM_VORTEX_TEMPEST 0x07d34b9f
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#define CPUFAMILY_ARM_LIGHTNING_THUNDER 0x462504d2
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/* The following synonyms are deprecated: */
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#define CPUFAMILY_INTEL_6_23 CPUFAMILY_INTEL_PENRYN
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#define CPUFAMILY_INTEL_6_26 CPUFAMILY_INTEL_NEHALEM
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#endif /* _MACH_MACHINE_H_ */
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